Anti-Tamper Digital Clocks Options
Anti-Tamper Digital Clocks Options
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Thus, the existing invention is not really intended to be restricted to the embodiments shown herein but is to be accorded the widest scope in line with the principles and novel capabilities disclosed herein.
suggests for evaluating that utilizes the plurality of delayed monotone signals to detect a voltage fault and
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twenty five. The strategy for detecting voltage tampering as defined in assert 23, wherein utilizing the clock to cause the Appraise circuit comprises employing a clock edge at an close in the Assess period of time to cause the Assess circuit.
an Consider circuit, activated through the clock, that uses the main plurality of delayed monotone alerts or the 2nd plurality of delayed monotone alerts to detect a clock fault.
The methods of a technique or algorithm explained in reference to the embodiments disclosed herein may be embodied straight in hardware, or in a mix of components along with a software program module executed by a processor. A application module may well reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, really hard disk, a removable disk, a CD-ROM, or every other method of storage medium known in the art.
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nine. The apparatus for detecting clock tampering as described in declare 8, further comprising: signifies for resetting the implies for delaying the monotone sign all through a reset time frame, whereby the reset time period is previous to the clock Assess period of time.
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A different element of the creation may reside within an apparatus for detecting clock tampering, comprising: initial circuit, a primary plurality of resettable hold off line segments, a next circuit, a 2nd plurality of resettable hold off line segments, and an Consider circuit. The main circuit supplies a first monotone signal all through a first clock Consider time frame related to a clock. The very first plurality of resettable hold off line segments Every hold off the very first monotone signal to deliver a respective 1st plurality of delayed monotone indicators. Resettable delay line segments concerning a resettable delay line section connected with a minimum hold off time and a resettable hold off line phase associated with a greatest delay time are Each and every connected to discretely growing delay occasions.
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A monotone sign is delivered all through an Consider time period. The monotone signal is delayed applying Every on the plurality of resettable hold off line segments to crank out a respective plurality of delayed monotone alerts. A clock is utilized to set off an Assess circuit that utilizes the plurality of delayed monotone indicators to detect a voltage fault.
The existing invention relates commonly to detecting tampering with the clock and/or supply voltage of a processor.